1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a semiconductor memory device having a configuration suited for high integration.
2. Description of the Background Art
Referring to FIG. 13, a prior art semiconductor memory device 700 includes regions 710, 720, 721 to 724, 730 and 740. The region 710 includes a memory cell array 711, a column decoder 712, a row decoder 713 and an input/output circuit zone 714.
The memory cell array 711 includes a plurality of memory cell blocks 716 and a plurality of sense amplifier groups 717. The memory cell blocks 716 and the sense amplifier groups 717 are arranged alternately in a column direction 725. A memory cell block 716 includes a plurality of memory cells arranged in column and row directions 725 and 726. A sense amplifier group 717 amplifies data outputted from a plurality of memory cells included in the memory cell block 716.
The column decoder 712 decodes a column address based on an address signal inputted from an address terminal (not shown) to select each of a plurality of bit line pairs (not shown) included in the memory cell array 711 according to the decoded column address. The row decoder 713 decodes a row address based on an address signal inputted from the address terminal to select each of a plurality of word lines (not shown) included in the memory cell array 711 according to the decoded row address.
The input/output circuit zone 714 includes a main amplifier 7141, a write driver 7142 and an output driver 7143. The main amplifier 7141 amplifies data outputted from a plurality of memory cells included in the memory cell array 711 to output the amplified data to the output driver 7143. The write driver 7142 writes data inputted from the input/output terminal (not shown) onto a plurality of memory cells included in the memory cell array 711. The output driver 7143 outputs data amplified by the main amplifier 7141 to the input/output terminal (not shown).
The regions 720, 730 and 740 are of the same configuration as the region 710. The regions 721 to 724 includes respective peripheral circuit groups each constituted of a control circuit, a set-up circuit, a step-down circuit, a redundancy circuit and others.
In the semiconductor memory device 700, each of the regions 710, 720, 730 and 740 includes one input/output circuit zone 714 at one end thereof.
The semiconductor memory device 700 is fabricated, for example, as a semiconductor memory device of a 2 bank configuration. In that case, the memory cell arrays 711 of the respective regions 710 and 720 constitutes a bank A, and the memory cell arrays 711 of the regions 730 and 740 constitute a bank B. Furthermore, the semiconductor memory device 700 is fabricated as a semiconductor memory device of 4 bank configuration. In that case, the memory cell array 711 of the region 710 constitutes a bank A, and the memory cell array 711 of the region 720 a bank B, the memory cell array 711 of the region 730 a bank C and the memory cell array 711 of the region 740 a bank D.
Hence, the prior art semiconductor memory device 700 includes a plurality of banks and is of a configuration including one input/output circuit zone provided in each bank.
FIG. 14 a circuit diagram representing part of the region 710 shown in FIG. 13. Sense amplifier groups 717A, 717B, 717C, 717D and 717E and memory cell blocks 716A, 716B, 716C and 716D are arranged alternately in the column direction.
Word line drivers 718A, 718B, 718C and 718D are placed adjacent to the respective memory cell blocks 716A, 716B, 716C and 716D. Besides, the word line drivers 718A, 718B, 718C and 718D activate word lines placed in the respective memory cell blocks 716A, 716B, 716C and 716D according to an row address from the row decoder 713. When each of the memory cell blocks 716A, 716B, 716C and 716D includes 8 word lines. The word line drivers 718A, 718B, 718C and 718D are each inputted with a 4 bit row address from the row decoder 713. The highest one bit of a 4 bit row address selects each of the memory cell blocks 716A, 716B, 716C and 716D and the lower three bits further selects 8 word lines in each of the memory cell blocks 716A, 716B, 716C and 716D which have been selected by the highest one bit.
The memory cell blocks 716A, 716B, 716C and 716D each include a plurality of memory cells M/C arranged in the row and column directions.
The memory cell blocks 716A, 716B, 716C and 716D are connected to the input/output circuit zone 714 through global input/output line pairs GIOA, GIOB, GIOC and GIOD.
When a plurality of memory cells M/C, M/C, . . . included in a group 716A1 of the memory cell block 716A are sequentially specified by the column decoder 712, the row decoder 713 and the word line driver 718A, a sense amplifier 717A1 amplifies data read out from each cell. Furthermore, the sense amplifier 717A1 outputs the amplified data to the input/output circuit zone 714 through the global input/output line pair GIOC. Moreover, a plurality of memory cells M/C, M/C, . . . included in a group 716A4 of the memory cell block 716A, likewise, are sequentially specified, a sense amplifier 717A2 amplifies data read out from each memory cell. Then, the sense amplifier 717A2 outputs the amplified data to the input/output circuit zone 714 through the global input/output line pair GIOD. Furthermore, the sense amplifiers 717A1 and 717A2 amplify data outputted from not only a plurality of memory cells included in the memory cell block 716A, but also a plurality of memory cells included in a memory cell block (not shown) residing in the opposed side from the memory cell block 716A, and output the amplified data to the input/output circuit zone 714 through the global input/output line pairs GIOC and GIOD.
Furthermore, when a plurality of memory cells M/C, M/C, . . . included in a group 716A2 of the memory cell block 716A are sequentially specified, a sense amplifier 717B1 amplifies data read out from each memory cell. Then the sense amplifier 717B1 outputs the amplified data to the input/output circuit zone 714 through the global input/output line pair GIOB. Besides, the sense amplifier 717B1 also amplifies data output from a plurality of memory cells M/C, M/C, . . . included in a group 716B2 of the memory cell block 716B and outputs the amplified data onto the global input/output line pair GIOB.
Furthermore, when a plurality of memory cells M/C, M/C, . . . included in a group 716A3 of the memory cell block 716A are sequentially specified, a sense amplifier 717B2 amplifies data read out from each memory cell. Then the sense amplifier 717B2 outputs the amplified data to the input/output circuit zone 714 through the global input/output line pair GIOA. Besides, the sense amplifier 717B2 also amplifies data output from a plurality of memory cells M/C, M/C, . . . included in a group 716B3 of the memory cell block 716B and outputs the amplified data onto the global input/output line pair GIOA.
Accordingly, data read out from a plurality of memory cells included in the memory cell block 716A are amplified by the sense amplifier group 717A or 717B and the amplified data are outputted to the input/output circuit zone 714 through the global input/output line pairs GIOA, GIOB, GIOC and GIOD.
This applies to a plurality of memory cells included in each of the other memory cell blocks 716B, 716C and 717D in a similar way.
Referring to FIG. 15, detailed description will be given of input/output of data to a memory cell. FIG. 15 shows a case where data is inputted/outputted with 4 bit as a unit. The group 716A1 of the memory block 716A includes a plurality of memory cells. The plurality of memory cells are connected to word lines WL00 to WL0n extending in the row direction and to bit line pair BL1 and /BL1 extending in the column direction. An N channel MOS transistor 731 is inserted in the bit line /BL1 and the N channel MOS transistor 732 is inserted in the bit line BL1. The N channel MOS transistors 731 and 732 are turned on/off by a control signal BLU0.
The sense amplifier 717A1 is connected between the bit line pair BL1 and /BL1. The bit line BL1 is connected to a local input/output line LIO00 through an N channel MOS transistor 734. The bit line /BL1 is connected to a local input/output line /LIO00 through an N channel MOS transistor 733. The N channel MOS transistors 733 and 734 are turned on/off in company with activation/deactivation of a column select line CSL0 connected to the column decoder 712.
The local input/output line LIO00 is connected to the global input/output line GIO1 through an N channel MOS transistor 735 and the local input/output line /LIO00 is connected to the global input/output line /GIO01 through an N channel MOS transistor 736. The N channel MOS transistors 735 and 736 are turned on/off by a control signal LIS00. Note that the N channel MOS transistors 735 and 736 constitutes a switch 719A connecting the local input/output line pair and the global input/output line pair therebetween.
The global input/output line pair GIO1 and /GIO1 are connected to the main amplifier 7141 and the write driver 7142. Besides, the output driver 7143 is connected to the main amplifier 7141.
The write driver 7142 is composed of inverters 737 to 740 P channel MOS transistors 741 and 743; and N channel MOS transistors 742 and 744. The P channel MOS transistor 741 and the N channel MOS transistor 742 are connected in series between a power source node and a ground node. Furthermore, the P channel MOS transistor 743 and the N channel MOS transistor 744 are connected in series between the power source node and the ground node.
The output driver 7143 is composed of a P channel MOS transistor 745; and an N channel MOS transistor 746. The P channel MOS transistor 745 and the N channel MOS transistor 746 are connected in series between the power source node and the ground node.
The main amplifier 7141 amplifies a potential difference between the global input/output line pair GIO1 and /GIO1 and outputs a resultant to the output driver 7143. The output driver 7143 outputs a signal of H (logical high) level or L (logical low) to an output pin DQ1 based on the potential difference outputted from the main amplifier 7141. When data is inputted to an input pin DIN1, the write driver 7142 provides a potential difference based on input data between the global input/output line pair GIO1 and /GIO1. When data [1] is inputted to the input pin DIN1, the inverter 737 outputs a signal of L level and the inverter 738 outputs a signal of H level. Furthermore, the inverter 739 outputs a signal of L level and the inverter 740 outputs a signal of H level.
As a result, the N channel MOS transistor 742 and the P channel MOS transistor 743 are turned off, while the P channel MOS transistor 741 and the N channel MOS transistor 744 are turned on. The write driver 7142 outputs a signal of H level onto the global input/output line GIO1 and a signal of L level onto the global input/output line /GIO1.
When data [0] is inputted to the input pin DIN1, the inverter 737 outputs a signal of H level and the inverter 738 outputs a signal of L level. Furthermore, the inverter 739 outputs a signal of H level and the inverter 740 outputs a signal of L level.
As a result, the P channel MOS transistor 741 and the N channel MOS transistor 744 are turned off, while the N channel MOS transistor 742 and the P channel MOS transistor 743 are turned on. The write driver 7142 outputs a signal of L level onto the global input/output line GIO1 and a signal of H level onto the global input/output line /GIO1.
Description will be given of reading out data from a plurality of memory cells included in the group 716A1 of the memory cell block 716A. The column select line CSL0 is activated by the column decoder 712. The word line driver 718A activates each of the word lines WL00 to WL0n according to a row address decoded by the row decoder 713. Furthermore, the N channel MOS transistors 731 and 732 are turned on by the control signal BLU0 from the control circuit (not shown) and the N channel MOS transistors 735 and 736 are turned on by the control signal LIS00 from the control circuit.
When the word line WL00 is activated and data [1] is outputted from a memory cell, the bit line /BL1 assumes a potential VCC/2+xcex1 slightly higher than a precharge potential VCC/2, while the bit line BL1 remains at the precharge potential VCC/2. The potential VCC/2+xcex1 on the bit line /BL1 is transmitted to the sense amplifier 717A1 through the N channel MOS transistor 733 and the potential VCC/2 on the bit line BL1 is transmitted to the sense amplifier 717A1 through the N channel MOS transistor 732. Then, the sense amplifier 717A1 raises the potential VCC/2+xcex1 on the bit line /BL1 to the power source potential VCC and lowers the potential VCC/2 on the bit line BL1 down almost to 0V. That is, the sense amplifier 717A1 amplifies a potential difference between the bit lines BL1 and /BL1. Then, the potential VCC on the bit line /BL1 is transmitted onto the local input/output line /LIO00 through the N channel MOS transistor 733 and the potential 0V on the bit line BL1 is transmitted to the local input/output LIO00 through the N channel MOS transistor 734.
The local input/output line /LIO00 outputs a potential VCCxe2x88x92(Vthn+xcex1) onto the global input/output line /GIO1 through the N channel MOS transistor 736 and the local input/output line LIO00 outputs a potential 0V onto the global input/output line GIO1 through the N channel MOS transistor 735. Then, the main amplifier 7141 further amplifies a potential difference between the global input/output line pair GIO1 and /GIO1 and outputs the potential 0V to the gate terminal of the P channel MOS transistor 745 and the potential VCCxe2x88x92(Vthn+xcex1) to the gate terminal of the N channel MOS transistor 746. Then, the P channel MOS transistor 745 and the N channel MOS transistor 746 are turned on, and the output driver 7143 outputs a signal of H level, that is data [1], to the output pin DQ1.
When data [0] is outputted from a memory cell connected to the word line WL00, potentials on the bit line pair BL1 and /BL1, the local input/output line pair LIO00 and /LIO00 and the global input/output line pair GIO0 and /GIO0 assume inverted potentials to the respective above described potentials and the inverted potentials are inputted to the main amplifier 7141. Then, the main amplifier 7141 outputs a potential VCCxe2x88x92(Vthn+xcex1) to the gate terminal of the P channel MOS transistor 745 and provides the potential 0V to the gate terminal of the N channel MOS transistor 746. Then, the output driver 7143 outputs a signal of L level, that is data [0], to the output pin DQ1.
Description will be given of writing data onto a plurality of memory cells included in the group 716A1 of the memory cell array 716A. When data [1] is inputted to the input pin DIN1, the write driver 7142, as described above, raises a potential on the global input/output line /GIO0 to the potential VCC while lowering a potential on the global input/output line GIO1 down to the potential 0V. The global input/output line /GIO1 inputs the potential VCC onto the local input/output line /LIO00 through the N channel MOS transistor 736 and the global input/output line GIO1 inputs the potential 0V onto the local input/output line LIO00 through the N channel MOS transistor 735. Then, the local input/output line /LIO00 inputs the potential VCC onto the bit line /BL1 through the N channel MOS transistor 733 and the local input/output line LIO00 inputs the potential 0V onto the bit line BL1 through the N channel MOS transistor 734.
The potential VCC on the bit line /BL1 is transmitted along the bit line /BL1 through the N channel MOS transistor 731 and written onto a memory cell activated by the word line WL00.
When data [0] is inputted to the input pin DIN1, potentials on the global input/output lime pair GIO1 and /GIO1, the local input/output line pair LIO00 and /LIO00 and the bit line pair BL1 and /BL1 assume inverted potentials to the respective above described potentials. Then, the data [0] is written onto a memory cell activated by the word line WL00.
Likewise, data outputted from each of a plurality of memory cells included in the group 716A2 of the memory cell block 716 is amplified by the sense amplifier 717B1 and the amplified data is outputted to the main amplifier and the output driver through a local input/output line pair LIO101 and /LIO01, a switch 719B and a global input/output line pair GIO2 and /GIO2. Besides, following a reverse route of the above described, data is written onto each of a plurality of memory cells included in the group 716A2 of the memory cell block 716A.
Furthermore, data outputted from each of a plurality of memory cells included in the group of 716A3 is amplified by the sense amplifier 717B2 and the amplified data is outputted to the main amplifier and the output driver through the local input/output line pair LIO01 and /LIO01, the switch 719B and the global input/output line pair GIO2 and /GIO2. Besides, following a reverse route of the above described, data is written onto each of a plurality of memory cells included in the group 716A3.
Furthermore, data outputted from each of a plurality of memory cells included in the group 716A4 is amplified by the sense amplifier 717A2 and the amplified data is outputted to the main amplifier and the output driver through the local input/output line pair LIO00 and /LIO00, the switch 719A and the global input/output line pair GIO1 and /GIO1. Besides, following a reverse route of the above described, data is written onto each of a plurality of memory cells included in the group 716A4.
FIG. 16 is a circuit diagram in a case where data is inputted/outputted with 2 bits as a unit. In the same operation as described above, data is inputted or outputted to or from a plurality of memory cells included in each of the memory cell blocks 716A, 716B, 716C and 716D.
In the prior art semiconductor memory device 700, however, the regions 710, 720, 730 and 740 are provided with 4 input/output circuit zones 714; therefore, when data increases in number of bits in the future, an occupancy area of input/output circuit zones is totally larger, resulting in a problem to hinder increase in integration.
Furthermore, since the 4 input/output circuit zones are gathered almost in the central portion of the semiconductor memory device 700, power consumption is locally concentrated, resulting again in a problem to hinder stable operations of adjacent circuits.
Moreover, since in the prior semiconductor memory device 700, data is inputted or outputted to or from each of plurality of memory cells included in one bank by one input/output circuit zone, power consumption in the input/output circuit zone increases, resulting still again in a problem to hinder reduction in power consumption.
It is accordingly an object of the present invention to provide a semiconductor memory device easy to achieve its high integration.
It is another object of the present invention to provide a semiconductor memory device capable of distributing power consumption across the device.
It is still another object of the present invention to provide a semiconductor memory device capable of realizing low power consumption even in its highly integrated state.
The present invention is directed to a semiconductor memory device having a plurality of regions, each of which includes first and second memory cell arrays arranged in a column direction, and an input/output circuit zone placed between the first and second memory cell arrays, wherein the input/output circuit zone inputs or outputs data to or from a plurality of memory cells included in each of the first and second memory cell arrays.
A semiconductor memory cell according to the present invention includes a plurality of regions obtained by division. Each of the plurality of regions includes first and second memory cell arrays and an input/output circuit zone placed between the first and second memory cell arrays. The input/output circuit zone inputs or outputs data to or from a plurality of memory cells included in the first memory cell array or the second memory cell array.
Hence, according to the present invention, since the input/output circuit zone inputting/outputting data is placed between the first and second regions in each of the plurality of regions obtained by division, the input/output circuit zones are distributed all over the semiconductor memory device. As a result, power consumption can be prevented from being locally concentrated. Furthermore, according to the present invention, the input/output circuit zone can be configured with a smaller number of circuits by inputting or outputting data to or from the first and second memory cell arrays in a selective manner. As a result, an occupancy area of the input/output circuit zone can be smaller.
In each of a plurality of regions of a semiconductor memory device, one bank is preferably constituted of the first and second memory cell arrays.
One bank is divided into first and second memory cell arrays and an input/output circuit zone is placed between the first and second memory cell arrays. Hence, according to the present invention, input/output circuit zones can be distributed in placement on a semiconductor memory device in which data is inputted to or outputted from each bank as a unit.
Each of first and second memory cell arrays included in a plurality of regions of a semiconductor memory device preferably constitutes one bank different from the other.
An input/output circuit zone is placed between banks. The input/output circuit zone inputs or outputs data to or from a plurality of memory cells included in one bank or the other bank. Hence, according to the present invention, input/output circuit zones can be distributed in placement on a semiconductor memory device of a 2 bank configuration.
It is preferable that a plurality of regions in a semiconductor memory device constitute a semiconductor memory device of a 4 bank configuration and each of the first and second memory cell arrays constitutes one bank different from the other.
For example, in a semiconductor memory device constructed from a bank A, a bank B, a bank C and a bank D, input/output circuit zones are placed between the banks A and B, and between the banks C and D, respectively. Hence, according to the present invention, input/output circuit zones can be distributed in placement on a semiconductor memory device of a 4 bank configuration.
It is preferable that data of n bits (n is a natural number) is inputted or outputted to or from each of a plurality of regions of a semiconductor memory device and an input/output circuit zone includes n input/output circuits for inputting or outputting data of n bits to or from a plurality of memory cells included in a first or second memory cell array.
The input/output circuit zone selectively inputs or outputs data of n bits as a unit to or from the first or second memory cell array. Each of a plurality of regions inputs or outputs data of n bits as a unit. Hence, according to the present invention, the number of the input/output circuits constituting an input/output circuit zone can be smaller. As a result, an occupancy area of the input/output circuit zone can be smaller.
Each of a plurality of regions of a semiconductor memory device preferably further includes a plurality of first local input/output line pairs for inputting or outputting data to or from each of a plurality of memory cells included in a first memory cell array, a plurality of second local input/output line pairs for inputting or outputting data to or from each of a plurality of memory cells included in a second memory cell array, a plurality of common global input/output line pairs connected to an input/output circuit zone, a plurality of first global input/output line pairs connected to the plurality of first local input/output line pairs, a plurality of second global input/output line pairs connected to the plurality of second local input/output line pairs, a plurality of first switches for connecting the plurality of common global input/output line pairs to a corresponding plurality of first global input/output line pairs, and a plurality of second switches for connecting the plurality of common global input/output line pairs to a corresponding plurality of second global input/output line pairs.
Data is inputted to or outputted from a plurality of memory cells included in the first memory cell array through a first local input/output line pair, a first global input/output line pair, a first switch and a common global input/output line pair. Furthermore, data is inputted to or outputted from a plurality of memory cells included in the second memory cell array through a second local input/output line pair, a second global input/output line pair, a second switch and a common global input/output line pair. Hence, data can be selectively inputted to or outputted from the first or second memory cell array by selectively turning on or off the first or second switch.
A plurality of first switches and a plurality of second switches are preferably placed between the first and second memory cell arrays.
The first switches and the second switches are placed between the first and second memory cell arrays together with an input/output circuit zone. Hence, according to the present invention, since the input/output circuit zone and the switches are collectively placed in one area, a total occupancy area of the switches and the input/output circuit zone can be smaller.
Each of a plurality of regions of a semiconductor memory device preferably further includes a first column decoder selecting a plurality of bit line pairs connected to a plurality of memory cells included in a first memory cell array, and a second column decoder selecting a plurality of bit line pairs connected to a plurality of memory cells included in a second memory cell array, wherein each of a plurality of first switches is turned on/off by a control signal from the first column decoder and each of a plurality of second switches is turned on/off by a control signal from the second column decoder.
A plurality of memory cells included in the first memory cell array are selected by the first column decoder and a plurality of memory cells included in the second memory cell array are selected by the second column decoder. A first switch is turned on/off by a control signal from the first column decoder and a second switch is turned on/off by a control signal from the second column decoder.
Hence, according to the present invention, a first switch can be turned on in synchronism with input or output of data to or from the first memory cell array and a second switch can be turned on in synchronism with input or output of data to or from the second memory cell array.
It is preferable that in a test mode, a first switch connecting a first global input/output line pair for inputting or outputting data to or from one memory cell selected arbitrarily from the first memory cell array and a common global input/output line pair corresponding to the first global input/output line pair therebetween is turned on, and a second switch connecting a second global input/output line pair for inputting or outputting data to or from a memory cell having the same address as the one memory cell among a plurality of memory cells included in the second memory cell array and a common global input/output line pair corresponding to the second global input/output line pair therebetween is turned on.
In the test mode, data are inputted to or outputted from a plurality of memory cells included in the first memory cell array and a plurality of memory cells in the second memory cell array simultaneously. Hence, according to the present invention, a test time can be reduced.
Furthermore, a semiconductor memory device according to the present invention has a plurality of regions and each of the plurality of regions includes first and second memory cell arrays arranged in a column direction, a column decoder placed between the first and second memory cell arrays, a first input/output circuit zone inputting or outputting data to or from a plurality of memory cells included in the first memory cell array, and a second input/output circuit zone inputting or outputting data to or from a plurality of memory cells included in the second memory cell array.
A semiconductor memory device according to the present invention includes a plurality of regions. Each of the plurality of regions includes first and second memory cell arrays, a column decoder placed between the first and second memory cell arrays, and first and second input/output circuit zones. That is, two input/output circuit zones are placed in each region. Hence, according to the present invention, input/output circuit zones can be distributed in placement. As a result, power consumption can be prevented from locally being concentrated. Besides, malfunction of adjacent circuits due to the local concentration in power consumption can be prevented from occurring.
In each of a plurality of regions of a semiconductor memory device, one bank is preferably constituted of first and second memory cell arrays.
Two input/output circuit zones are provided in one bank. Hence, according to the present invention, input/output circuit zones can be distributed in placement on a semiconductor memory device inputting/outputting data with each bank as a unit. As a result, local concentration of power consumption can be prevented from occurring. Besides, malfunction of adjacent circuits due to local concentration of power consumption can be prevented from occurring.
Each of first and second memory cell arrays included in a plurality of regions of a semiconductor memory device preferably constitutes one bank different from the other.
A first input/output circuit zone inputs or outputs data to or from a plurality of memory cells included in one bank. A second input/output circuit zone inputs or outputs data to or from a plurality of memory cells included in the other bank. Hence, according to the present invention, a configuration can be realized which is suited for banks each inputting or outputting data to or from itself independently and simultaneously, in which distribution of input/output circuit zones in placement can be effected.
It is preferable that a plurality of regions in a semiconductor memory device constitute a semiconductor memory device of a 4 bank configuration and each of the first and second memory cell arrays constitutes one bank different from the other.
For example, in a semiconductor memory device of a 4 banks including a bank A, a bank B, a bank C and a bank D, one input/output circuit zone is provided to each of the banks A, B, C and D. Furthermore, each of the banks A, B, C and D performs supply and reception of data on an individual input/output circuit zone. Hence, according to the present invention, in a semiconductor memory device of a 4 bank configuration, distribution of input/output circuit zones in placement, suited for the bank configuration can be realized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.